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JULY 2000
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER
GENERAL DESCRIPTION
The XRT71D00 is a single channel, single chip Jitter Attenuator, that meets the Jitter requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR253 standards. In addition, the XRT71D00 also meets the Jitter and Wander specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards for Desynchronizing and Pointer adjustments in the DS3 to STS-SPE mapping applications. FEATURES * Meets the E3/DS3/STS-1 jitter requirements * No external components required * Compliance with jitter transfer template outlined in ITU G.751, G.752, G.755 and GR-499-CORE,1995 standards BLOCK DIAGRAM OF THE XRT71D00 * Meets output jitter requirement as specified by ETSI TBR24 * Meets the Jitter and Wander specifications described in T1.105.03b,GR-253 and GR-499 standards. * Selectable buffer size of 16 and 32 bits * Jitter attenuator can be disabled * Available in a 32 pin TQFP package. * Single 3.3V or 5.0V supply. * Operates over - 400 C to 850 C temperature range. APPLICATIONS * E3/DS3 Access Equipment. * STS-SPE to DS3 Mapper * DSLAMs
BW S
M C lk
T im in g C on tro l B lo c k / P h a s e lo c k ed L oo p
IC T DJA R C lk C lk E S RPOS RNEG
W rite C lock R ead C lock R R C lk RRPO S
1 6 /3 2 B it F IF O
RRNEG FL
H O S T/H W RST D S 3/E 3
M ic ro p ro c es s o r S e ria l In te rfa ce
CS SDI
SDO
S C lk
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER
XRT71D00
REV. 1.01
PIN OUT OF THE XRT71D00 (32 LEAD TFQP PACKAGE)
E3 / DS3 / CS
C h_ A ddr_0
R R P OS
R P OS
VDD
VDD
NC
32
25
NC
NC RNEG R C lk GND M C lk GND VDD S TS -1
1
24
NC RRNEG R R C lk GND IC T RST D JA /S D O
8
17
NC
9
16
C lkE S /S D I
B W S /C h_A d dr_ 1
FS S /S C lk
NC
NC
FL
ORDERING INFORMATION
PART NUMBER XRT71D00IQ PACKAGE 32 Lead TQFP OPERATING TEMPERATURE RANGE -400C to +850C
H O ST/H W
2
NC
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PRELIMINARY
1 1 1 2
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... APPLICATIONS .............................................................................................................................................. BLOCK DIAGRAM OF THE XRT71D00 ............................................................................................................ PIN OUT OF THE XRT71D00 (32 LEAD TFQP PACKAGE) ..............................................................................
ORDERING INFORMATION ............................................................................................... PIN DESCRIPTIONS .......................................................................................................... ELECTRICAL CHARACTERISTICS .................................................................................. SYSTEM DESCRIPTION ....................................................................................................
2 3 6 8
Figure 1. Illustration of the XRT71D00 ( configured to operate in the "Hardware" Mode) .....................8 Figure 2. Illustration of the XRT71D00(configured to operate in the "Host" Mode) ................................. 9 BACKGROUND INFORMATION: ........................................................................................................................ 9 Figure 3. Category 1 DS3 Jitter Transfer Mask ..........................................................................................10 JITTER ATTENUATION: .......................................................................................................................... 10 Figure 4. XRT71D00 Desynchronizer Block Diagram ................................................................................ 11 TABLE 1: FUNCTIONS OF DUAL MODE PINS IN "HARDWARE" MODE CONFIGURATION ......................................... 11 TABLE 2: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ............................................................. 12 Figure 5. Microprocessor Serial Interface Data Structure .........................................................................13 Figure 6. Timing Diagram for the Microprocessor Serial Interface .......................................................... 13 Figure 7. Input/Output Timing ......................................................................................................................14 TABLE 3: XRT71D00 JITTER TRANSFER FUNCTION ......................................................................................... 14 TABLE 4: XRT71D00 MAXIMUM JITTER TOLERANCE ........................................................................................ 15
PACKAGE INFORMATION .............................................................................................. 16
32 LEAD TQFP PACKAGE DIMENSIONS ....................................................................................... 16 ORDERING INFORMATION ............................................................................................................. 16
REVISIONS ....................................................................................................................... 17
III
PIN # 1 2 3 4 5
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
XRT71D00
REV. 1.01
PIN DESCRIPTIONS
PIN DESCRIPTION
NAME NC RNEG TYPE *** I DESCRIPTION
This pin is not connected internally Receive Negative Data (Jittery)
The input jittery negative data is sampled either on the rising or falling edge of RClk depending on the setting of ClkES (pin 10). If ClkES is "high", then RNEG will be sampled on the falling edge of RClk. If ClkES is "low", then RPOS will be sampled on the rising edge of RClk. This pin is typically tied to the "RNEG" output pin of the LIU.
RClk GND MClk
I *** I
Receive Clock (Jittery)
Clock input RClk should be connected to the recovered clock. Digital Ground
Master Clock Input.
Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/20ppm. This clock must be continuous and jitter free with duty cycle between 30 to 70%. NOTE: It is permissible to use the EXClk signal orSTS-1 clock.
6 7 8
GND VDD STS-1
*** *** I
Analog Ground Analog Positive Supply: 3.3V or 5.0V 5%
SONET STS-1 Mode Select:
This pin along with the E3/DS3* select pin (pin 29) configures the XRT71D00 either in E3, DS3 or STS-1 mode. A table relating to the setting of the pins is given below: STS-1 E3/DS3* XRT71D00 Operating Mode 0 0 DS3 (44.736 MHz) 0 1 E3 (34.368 MHz) 1 0 STS-1 (51.84 MHz) 1 1 E3 (34.368 MHz) NOTES: 1. This input pin is active only in the Hardware Mode 2. Internal 50 K Ohm pull-up resistor.
9 10
NC ClkES/(SDI)
*** I
This pin is not connected internally Clock Edge Select Input/Serial Data Input Pin.
The function of this pin depends on whether XRT71D00 is configured in Harware or Host Mode.
Hardware Mode--Clock Edge Select Input
The status of this pin determines the sampling edge on RClk to RPOS/ RNEG and RRPOS/RRNEG data update on RRClk edge. When high: RPOS/RNEG is sampled on falling edge of RClk and RRPOS/RRNEG is updated on rising edge of RRClk. When low: RPOS/RNEG is sampled on rising edge of RClk and RRPOS/RRNEG is updated on falling edge of RRClk.
Host Mode--Serial Data Input
The address value (of the command registers) or the data value is either Read or Written through this pin. The input data will be sampled on the rising edge of the SClk pin (pin 11).
4
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
PIN DESCRIPTION
PIN # 11 NAME FSS/(SClk) TYPE I DESCRIPTION
FIFO Size Select Input/Serial Clock Input.
The function of this depends on whether XRT71D00 is configured in Hardware or Host mode.
Hardware Mode--FIFO Size Select Input
When high: Selects 32 bits FIFO. When low: Selects 16 bits FIFO.
Host Mode--Microprocessor Serial Interface Clock Signal
This signal will be used to (1) sample the data, on the SDI pin, on the rising edge of this signal. Additionally, during "Read" operations, the Microprocessor Serial Interface will update the SDO output on the falling edge of this signal. 12 HOST/HW I
Host/Hardware Mode Select:
An active-high input enables the Host mode. Data is written to the command registers to configure the XRT71D00. In the Host mode, the states of discrete input pins are inactive. An active-low input enables the Hardware Mode.In this mode, the discrete inputs are active.
13 14
NC FL
*** O
This pin is not connected internally. FIFO Limit.
This output pin is driven high whenever the internal FIFO comes within two-bits of being completely full.
15
BWS/ Ch_Addr_1
I
Bandwidth Select Input/Channel Addr_1 Assignment Input.
The function of this input pin depends on whether XRT71D00 is configured in Host or Hardware mode.
Hardware Mode--Bandwidth Select Input:
Connect this pin high to select wide jitter transfer bandwidth, and connect low to select narrow jitter transfer bandwidth.
Host Mode--Channel_Addr_1 Assignment Input:
This input pin, along with pin 28 permits the user to assign a "Channel Address" to the XRT71D00 device. 16 17 18 NC NC DJA/ (SDO) *** *** I/(O)
This pin is not connected internally. This pin is not connected internally. Disable Jitter Attenuator Input/Serial Data Output pin:
The function of this pin depends on whether XRT71D00 is configured in Host or Hardware mode.
Hardware Mode--Disable Jitter Attenuator:
An active-high disables the Jitter Attenuator.The RPOS/RNEG and RClk will be passed through without jitter attenuation.
Host Mode--Serial Data Output:
This pin will serially output the contents of the specified Command Register, during "Read" Operations. The data, on this pin, will be updated on the falling edge of the SClk input signal. This pin will be tri-stated upon completion of data transfer. NOTE: The user is advised to tie this pin to GND, if the XRT71D00 has been configured to operate in the "HOST" Mode. 19 RST I
Reset Input. (Active-Low)
A high-low transition will re-center the internal FIFO, and will clear the Command Registers (for Host Mode operation). Resetting this pin may corrupt data within the device. For normal operation, pull this pin to VDD.
5
PIN # 20 21 22 23 24 25 26
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
XRT71D00
REV. 1.01
PIN DESCRIPTION
NAME ICT TYPE I DESCRIPTION
In Circuit Testing Input. Active low. With this pin tied to ground, all output pins will be in high impedance mode for in-circuit-testing. For normal operation this input pin should be tied to VDD.
Digital Ground:
GND RRClk
*** O
Receive Output (De-jittered) Clock.
Output the de-jittered or smoothed clock if the jitter attenuator is enabled. The de-jittered data, RRPOS/RRNEG are clocked to this signal. If ClkES is "low", RRPOS/RRNEG will be updated at the falling edge of RRClk. If ClkES is "high", RRPOS/RRNEG will be updated at the rising edge of RRClk.
RRNEG
O
Receive Negative Data (De-Jittered) Output.
De-jittered negative data output. Updated on the rising or falling edge of RRClk, depending upon the state of the ClkES input pin (or bit-field setting).
NC NC RRPOS
*** *** O
This pin is not connected internally. This pin is not connected internally. Receive Positive Data (De-Jittered) Output.
De-jittered positive data output. Updated on the rising or falling edge of RRClk (see pin 9), depending upon the state of the ClkES input pin (or bitfield setting).
27 28
VDD Ch_Addr_0
*** I
Digital Positive Supply Voltage: 3.3V or 5.0V 5%
Channel Addr_0 Assignment Input.
This input pin, along with pin 15 permits the user to assign a "Channel Address" to the XRT71D00.
29
E3/DS3 (CS)
I
E3/DS3 Select Input/Chip Select Input:
The function of this pin depends on whether the XRT71D00 is configured in Host or Hardware mode.
Hardware Mode--E3/DS3* Select Input:
This pin along with the STS-1 mode select pin (pin 8) selects the operating mode. The following table provides the configuration: STS-1 0 0 1 1 E3/DS3* 0 1 0 1 XRT71D00 Operating Mode DS3 (44.736 MHz) E3 (34.368 MHz) STS-1 (51.84 MHz) E3 (34.368 MHz)
HOST Mode--Chip Select Input:
An active-low input enables the serial interface. (Note: This pin is internally pulled "high".) 30 31 VDD RPOS *** I Digital Positive Supply Voltage: 3.3V or 5.0V 5%
Receive Positive Data (Jittery) Input.
Data that is input on this pin is sampled on either the rising or falling edge of RClk depending on the setting of the ClkES pin (pin 10). If ClkES is "high", then RPOS will be sampled on the falling edge of RClk. If ClkES is "low", then RPOS will be sampled on the rising edge of RClk.
32
NC
***
This pin is not connected internally.
6
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
MAX 70 UNITS. % MHz MHz MHz 70 400 % ppm ns ns ns ns ns ns
ELECTRICAL CHARACTERISTICS
AC Electrical Characteristics
SYMBOL MClk MClk MClk MClk RClk RClk RClk RClk tsu th td te Duty Cycle Frequency E3 Frequency DS3 Frequency STS-1 Duty Cycle Frequency Rise Time Fall Time
PARAMETER
MIN 30
TYP 50 34.368 44.736 51.84
30 (E3,DS3 or STS-1) -400
50 0
RPOS/RNEG to RClk rise time setup RPOS/RNEG to RClk rising hold time RRPOS/RRNEG delay from RRClk rising RRPOS/RRNEG delay from RRClk falling
5 5 5 5
Microprocessor Serial Interface Timing ( see Figure 6)
SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32
PARAMETER CSB Low to Rising Edge of SClk Setup Time SClk to CSB Hold Time SDI to Rising Edge of SClk Setup Time SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period SClk to CSB Hold Time CSB "Inactive" Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Falling Edge of SClk, or rising edge of CSB to High Z
MIN 50 20 50 50 240 240 500 50 250
TYP
MAX
UNITS. ns ns ns ns ns ns ns ns ns
200 100 100
ns ns ns
7
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
XRT71D00
REV. 1.01
DC Electrical Characteristics (TA = 25 0C, VDD = 3.3 V 5 % unless otherwise specified)
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH=-5mA Output Low Voltage @ IOL=5mA Supply Current ( E3) Supply Current ( DS3 ) Supply Current ( STS-1) Input Leakage Current(except Input pins with Pull-up resistor. Input Capacitance Output Load Capacitance SYMBOL VDD VIH VIL VOH VOL Icc Icc Icc IL CI CL 5.0 25 36 40 40 41 TBD 10 A pF pF MIN 3.135 2.0 -0.5 2.4 0.4 52 43 TYP 3.3 MAX 3.465 5.25 0.8 UNITS V V V V V mA mA
DC Electrical Characteristics (TA = 25 0C, VDD = 5.0 V 5 % unless otherwise specified)
PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH=-5mA Output Low Voltage @ IOL=5mA Supply Current ( E3) Supply Current ( DS3 ) Supply Current ( STS-1) Input Leakage Current(except Input pins with Pull-up resistor. Input Capacitance Output Load Capacitance SYMBOL VDD VIH VIL VOH VOL Icc Icc Icc IL CI CL 5.0 25 36 40 40 41 TBD 10 A pF pF MIN 4.75 2.0 -0.5 2.4 0.4 52 43 TYP 5.0 MAX 5.25 5.25 0.8 UNITS V V V V V mA mA
ABSOLUTE MAXIMUM RATINGS:
Supply Range ESD Rating Operating Temperature Storage Temperature -0.5 V to + 6.0 V > 2000 V on all pins -400C to +850C -65C to + 150C
8
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
MClk
SYSTEM DESCRIPTION
The XRT71D00 is an integrated E3/DS3/STS-1 jitter attenuator that attenuates the jitter from the input clock and data.The jitter attenuation performance meets the latest specifications such as Bellcore GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T G.751,ITUT G.752 and ITU-T G.755 standards. In addition, the XRT71D00 also meets both the "mapping" and "pointer adjustment" jitter generation criteria for both Category I and Category II interfaces as specified in Bellcore GR-253.
The XRT71D00 also meets the DS3 wander specification that apply to SONET and asynchronous interfaces as specified in the ANSI T1.105.03b 1997 standard. Additionally, to support loop-timing applications, the XRT71D00 device can also be used to reduce and limit the amount of jitter in the recovered line clock signal. Figure 1 presents a simple block diagram of the XRT71D00 device, when it is configured to operate in the "Hardware" Mode and Figure 2 presents a simple block diagram of the XRT71D00 device, when it is configured to operate in the "Host" Mode.
FIGURE 1. ILLUSTRATION OF THE XRT71D00 ( CONFIGURED TO OPERATE IN THE "HARDWARE" MODE)
BWS
Jittery Clock
Timing Control Block / Phase locked Loop
ICT DJA RClk ClkES RPOS RNEG
FSS HOST/HW RST DS3/E3
Smoothed Clock
Write Clock
Read Clock
RRClk RRPOS
16/32 Bit FIFO
RRNEG FL
9
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
XRT71D00
REV. 1.01
FIGURE 2. ILLUSTRATION OF THE XRT71D00(CONFIGURED TO OPERATE IN THE "HOST" MODE)
Jittery Clock ICT
Timing Control Block / Phase locked Loop
MClk Smoothed Clock
RClk
Write Clock
Read Clock
RRClk RRPOS
16/32 Bit FIFO RPOS RNEG
RRNEG FL
HOST/HW RST
Microprocessor Serial Interface
CS
SDI
SDO SClk
The XRT71D00 DS3/E3 Jitter Attenuator IC consists of the following functional blocks: * Timing Control Block * The "Jitter-Attenuator" PLL * The "2-Channel 16/32 Bit FIFO". BACKGROUND INFORMATION: DEFINITION OF JITTER One of the most important and least understood measures of clock performance is jitter. The International Telecommunication Union defines jitter as "short term variations of the significant instants of a digita signal from their ideal positions in time". Jitter can occur due to any of the following: 1) Imperfect timing recovery circuit in the system 2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion SONET STS-1 to DS3 MAPPING SONET equipment jitter criteria are specified as: i) Jitter Transfer ii) Jitter Tolerance iii) Jitter Generation JITTER TRANSFER CHARACTERISTICS: The primary purpose of jitter transfer requirements is to prevent performance degradations by limiting the accummulation of jitter through the system such that it does not exceed the network interface jitter requirements. Thus, it is more important that a system meet the jitter transfer criteria for relatively high input jitter amplitudes. The jitter transferred through the system must be under the jitter mask for any input jitter amplitude within the range as shown in Figure 3
10
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
FIGURE 3. CATEGORY 1 DS3 JITTER TRANSFER MASK
0.1
Jitter Gain (dB)
slope = -20 dB/decade Acceptable Range
40 Frequency (Hz)
JITTER TOLERANCE: The jitter tolerance in the network element is defined as the maximum amount of jitter in the incoming signal that it can receive in an "error-free"manner. JITTER GENERATION: Jitter generation is defined in Section 7.3.3 of GR499-CORE. Jitter generation criteria exists for both Category I and II interfaces, which consist of "mapping" and "pointer adjustment" jitter generation. Mapping jitter is the sum of the intrinsic payload mapping jitter and the jitter that is generated as a result of the bit stuffing mechnisms used in all of the asynchronous DSn mapping into STS SPE. JITTER ATTENUATION: A digital Jitter Attenuation loop combined with the FIFO provides Jitter attenuation. The Jitter Attenuator requires no external components except for the reference clock. Data is clocked into the FIFO with the associated clock signal (TClk or RClk) and clocked out of the FIFO with the dejittered clock and data. When the FIFO is within 2 bits of being completely full, the FIFO Limit (FL) will be set.
In Figure 1 and Figure 2, this "de-jittered" clock is labeled "Smoothed Clock". This "Smoothed Clock" is now used to "Read Out" the "Recovered Data" from the 16/32 bit FIFO. This "Smoothed Clock" will also be output to the Terminal Equipment via the "RRClk" output pin. Likewise, the "Smoothed Recovered Data" will output to the Terminal Equipment via the RRPOS and RRNEG output pins. The XRT71D00 device is designed to work as a companion device with XRT7300 (STS-1/DS3/E3) Line Interface Unit. .ETSI TBR24 specifies the maximum output jitter in loop timing must be no more than 0.4UIpp when measured between 100Hz to 800KHzwith upto 1.5UI input jitter at 100Hz.. This means a jitter attenuator with bandwidth less than 100Hz is required to be compliant with the standard. ITU G.751 is another application where low bandwidth jitter attenuator is needed to smooth the gapped clock output in the de-multiplexer system. SONET STS-1 DS3 MAPPING: Bellcore GR-253 section 3.4.2 and the ANSI T1.105199 describes the asynchronous mapping for DS3 into STS-1 SPE.
11
S T S -N
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
XRT71D00
REV. 1.01
An asynchronous mapping for DS3 into STS-1 SPE is defined for clear-channel transport of DS3 signals that meet the DSX-3 requirements in the GR-499CORE. When the input data has a rate lower than the output data rate, the positive stuffing will occur. The stuffing mechanism that generates the C-bits is implemented in a desynchronizer that has the jitter output less than 0.4 UIpp assuming no jitter or wander at the input of the synchronizer and no pointer adjustments. A
block diagram of the Desynchronizer is shown in Figure 4. The elastic store accepts the STS-1 data stream and a gapped clock. The gaps in the input clock inhibit the elastic store from writing all but DS3 payload data. The bit leaking circuit stores incoming STS-1 pointer adjustments into a queue and leaks them out of the desynchronizer one bit at a time. STS-Nc signal is used to transport higher rate signals. However,the digital signals that SONET carries do not fit in the SPE perfectly.
FIGURE 4. XRT71D00 DESYNCHRONIZER BLOCK DIAGRAM
S T S -1 re fe r e n ce c lo ck S T S -1 g a p p e d c lo c k XR T71D00
S T S -N C lo c k C lo c k R e c o v e ry D e s c ra m b le / Dem ux
S T S -1 OH P ro c e s s in g
D S 3 p a ylo a d (d e jitte re d ) S T S -1 P o in te r P ro c e s s in g S T S -1 E la s tic S to re
S e c tio n & L in e O v e rh e a d
S T S -N
N th S T S -1 S T S -1 g a p p e d c lo c k D e jitte rin g & P o in te r A d ju s tm e n t
S tu ff C o n tro l
Hardware Mode The Host/HW pin (pin 12) is used to select the operating mode of the XRT71D00. In Hardware mode (connect this pin to ground), the serial processor interface is disabled and hardwired pins are used to control configuration and report status.. TABLE 1: FUNCTIONS OF DUAL MODE PINS IN "HARDWARE" MODE CONFIGURATION
PIN # 10 11 15 18 28 29 PIN NAME ClkES (SDI) FSS (SClk) BWS/Ch_Addr_1 DJA/(SDO) Ch_Addr_0 E3/DS3/(CS) FUNCTION, WHILE IN THE HARDWARE MODE ClkES FSS BWS DJA None E3/DS3
HOST MODE: In Host mode ( connect this pin to VDD), the serial port interface pins are used to control configuration and status report. In this mode, serial interface pins : SDI, SDO,SClk and CS are used. A listing of these Command Registers, their Addresses, and their bit-formats are listed below in Table 2.
12
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
D1 ClkES *** ClkES *** ClkES *** D0 FSS FL FSS FL FSS FL
TABLE 2: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS
ADDR 0X06 0x07 0x0E 0x0F 0x16 0x17 COMMAND CH_ADDR CH_ADDR REGISTER _1 _0 CR6 CR7 CR14 CR15 CR22 CR22 0 0 0 0 1 1 0 0 1 1 0 0 TYPE R/W RO R/W RO R/W RO D6 STS-1 *** STS-1 *** STS-1 *** D5 0 *** 0 *** 0 *** D4 E3/DS3* *** E3/DS3* *** E3/DS3* *** D3 DJA *** DJA *** DJA *** D2 BWS *** BWS *** BWS ***
* The serial interface for both the XRT71D00 and the XRT7300, XRT7302 and XRT7303, E3/DS3/STS-1 LIU which makes it easy to configure both the XRT71D00 and the LIU with a single CS, SDI, SDO and SClk input and output pins. SERIAL INTERFACE OPERATION. Serial interface data structure and timings are provided in Figure 5 and 6 respectively.. The clock signal is provided to the SClk and the CS is asserted for 50 ns prior to the first rising edge of the SClk. BIT 1--"R/W" (READ/WRITE) BIT This bit will be clocked into the SDI input, on the first rising edge of SClk (after CS has been asserted). This bit indicates whether the current operation is a "Read" or "Write" operation. A "1" in this bit specifies a "Read" operation; whereas, a "0" in this bit specifies a "Write" operation. Bits 2 through 5: The five (5) bit Address Values (labeled A0, A1, A2 ,A3,and A4) The next four rising edges of the SClk signal will clock in the 5-bit address value for this particular Read (or Write) operation. The address selects the Command Register for reading data from, or writing data to. The address bits to the SDI input pin is applied in ascending order with the LSB (least significant bit) first. BIT 7: A5 must be set to "0", as shown in Figure 5.
BIT 8--A6 The value of "A6" is a "don't care". Once these first 8 bits have been written into the Serial Interface, the subsequent action depends upon whether the current operation is a "Read" or "Write" operation. READ OPERATION Once the last address bit (A4) has been clocked into the SDI input, the "Read" operation will proceed through an idle period, lasting three SClk periods. On the falling edge of SClk Cycle #8 (see Figure 5) the serial data output signal (SDO) becomes active. At this point the user can begin reading the data contents of the addressed Command Register (at Address [A4,A3, A2, A1, A0]) via the SDO output pin. The Serial Interface will output this seven bit data word (D0 through D6) in ascending order (with the LSB first), on the falling edges of the SClk . The data (on the SDO output pin) is stable for reading on the very next rising edge of the SClk . WRITE OPERATION Once the last address bit (A4) has been clocked into the SDI input, the "Write" operation will proceed through an idle period, lasting three SClk periods. Prior to the rising edge of SClk Cycle #9 , eight bit data word is applied to SDI input. Data on SDI is latched on the rising edge of SClk.
13
CS SDI SDO
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
XRT71D00
REV. 1.01
FIGURE 5. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE
SClk
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A0
A1
A2
A3
A4
0
A6
D0
D1
D2
D3
D4
D5
D6
D7
High Z
D0 D1 D2 D3 D4 D5 D6 D7
High Z
NOTES: 1. 2. 3. 4.
A5 is always "0". R/W = "1" for "Read" Operations R/W = "0" for "Write" Operations Denotes a "don't care" value (shaded areas)
SIMPLIFIED INTERFACE OPTION The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading data from and/or writing data to this "combined" signal. This simplification is possible because only one of these signals are active at any given time. The inactive signal will be tri-stated.
FIGURE 6. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t29 CS t22 SClk t23 SDI t24 R/W A0 A1 t25 t21 t27 t26 t28
CS
SClk t30 SDO Hi-Z D0 t31 D1 Hi-Z t33 D2 D7 t32
SDI
14
XRT71D00
REV. 1.01
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
te
FIGURE 7. INPUT/OUTPUT TIMING
ts u RCLK th RPOS/RNEG RPOS/RNEG ClkES = 0 RCLK td
ts u RCLK th RPOS/RNEG RPOS/RNEG ClkES = 1 RCLK
Table 3 summarizes the results of jitter transfer characteristics testing, performed on the XRT71D00.
Table 4 summarize4s the results of jitter tolerance testing, performed on the XRT71D00.
TABLE 3: XRT71D00 JITTER TRANSFER FUNCTION
APPLICATION BWS INPUT JITTER FREQ. (HZ) 5 10 20 30 40 50 60 80 100 125 150 200 300 500 >1000 0.02 -0.10 -2.04 -3.63 -5.98 -7.55 -9.57 -12.54 -14.67 -16.67 -17.32 -18.77 -21.43 -22.22 -25.42 LOW 1UIPP Jitter Gain (dB) -0.33 -0.10 -0.24 -0.35 -0.53 -1.00 -1.46 -2.25 -3.07 -3.88 -5.74 -7.75 -12.04 -16.74 -21.13 0.36 -0.30 -2.24 -4.33 -6.16 -7.82 -9.17 -11.28 -13.36 -14.91 -16.78 -18.96 -21.81 -26.09 -33.44 0.06 -0.01 -0.13 -0.36 -0.72 -1.12 -1.66 -2.64 -3.52 -4.76 -5.89 -7.90 -10.89 -14.98 -20.66 0.44 -0.15 -3.16 -5.51 -7.68 -10.36 -12.50 -15.20 -16.22 -17.38 -19.45 -20.36 -22.96 -23.78 -23.51 HIGH DS3 LOW 10UIPP HIGH LOW 1UIPP Jitter Gain (dB) 0.37 0.20 0.35 0.05 -0.68 -1.15 -2.53 -3.56 -4.69 -5.78 -7.43 -10.71 -13.58 -17.66 -20.96 0.83 -0.22 -3.24 -5.93 -7.99 -9.61 -11.27 -13.59 -15.51 -17.07 -18.75 -21.11 -24.46 -28.84 -35.77 0.04 -0.02 -0.32 -0.73 -1.24 -1.85 -2.45 -3.76 -5.02 -6.50 -7.74 -9.94 -13.23 -17.16 -23.35 HIGH E3 LOW 10UIPP HIGH
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APPLICATION BWS FIFO SIZE FREQ. (HZ) 10 20 30 40 50 60 80 100 125 150 200 300 500 >1000
E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER
XRT71D00
REV. 1.01
TABLE 4: XRT71D00 MAXIMUM JITTER TOLERANCE
DS3 LOW 16 UI (PEAK TO PEAK) 34.313 21.439 18.314 16.939 16.314 16.064 15.689 15.439 15.439 15.314 15.314 15.189 15.189 15.0189 >64 >64 46.313 36.188 30.314 26.689 22.314 20.064 18.439 17.564 16.464 15.814 15.439 15.189 >64 43.188 36.813 34.313 33.188 32.563 31.814 31.439 31.314 31.189 31.064 30.939 30.939 30.939 >64 >64 >64 >64 60.313 53.188 44.813 40.434 37.313 35.438 33.563 32.063 31.314 30.939 26.689 18.564 16.689 16.064 15.689 15.564 15.314 15.314 15.189 15.189 15.189 15.064 15.064 15.189 HIGH LOW 32 HIGH LOW 16 UI (PEAK TO PEAK) >64 52.188 36.688 29.314 25.064 22.564 19.689 18.064 17.064 16.564 15.939 15.564 15.314 15.189 53.313 37.438 33.938 32.688 32.063 31.689 31.314 31.189 31.064 31.064 30.939 30.939 30.939 30.939 >64 >64 >64 58.438 50.438 45.438 39.688 36.813 34.813 33.688 32.438 31.564 31.189 30.939 HIGH E3 LOW 32 HIGH
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XRT71D00
E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESCYNCHRONIZER
PACKAGE INFORMATION 32 LEAD TQFP PACKAGE DIMENSIONS
ORDERING INFORMATION
PART NUMBER XRT71D00IQ PACKAGE 32 Lead TQFP OPERATING TEMPERATURE RANGE -400C to +850C
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XRT71D00 E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESCYNCHRONIZER REVISIONS
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2000 EXAR Corporation Datasheet February 2000 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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